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@@ -59,11 +59,14 @@ them are the ORIGINAL plan and carry expectations that measurement later correct
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kernel-scale runs each corrected the design (WAL file ≠ WAL backlog;
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cgroup cache credit; pool net-negative at 2 cores; parse floor). The
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2c/6GB envelope already improved 26.4 → 21.6min with counts byte-exact.
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- Record runs DONE (§7a.2): 2c/6GB **20.4min (R6 −23%), WAL 1.57GB (−14×)**;
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- 8c/7GB **18.3min, NO OOM, WAL 1.09GB** — all byte-exact. The <10min
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- target is NOT met and the gap is named: resolution is CORE-INVARIANT
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- (835.9s on 8 cores ≈ 812.5s sequential on 2) — the next arc profiles the
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- per-ref main-thread path, then cFnPtrEdges (86% of synthesis), then R7a.
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+ Record runs DONE (§7a.2): 2c/6GB 20.4min, 8c/7GB 18.3min NO-OOM — byte-exact.
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+ Batch-loop profile round DONE (§7a.3, #1339): countGuard quadratic killed,
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+ 19.3min. cFnPtr round DONE (§7a.4, #1341): 2.07× standalone, edge set
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+ hash-identical, envelope **17.6min (R6 −33%)**. The <10min-on-8c target
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+ remains open; levers left, ranked: **R7a C/C++ port (parse 338s — the
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+ last big rock)** > backpressure ~120s (checkpoint I/O floor) > E-scan/
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+ settle/read-mapping (~70–90s each, approaching honest work) > the 8c
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+ re-run formality (est. ~15.5min).
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- [ ] **R7a. C/C++ port** — biggest single-language effort; unlocks cg1212's parse
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expectation (6.2m → ~1.5–2m, 23% of that wall) + CARLA/UE/llvm-class repos;
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Metal + CUDA ride along (their blanking pre-passes stay TS-side — `preParse`
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Colby Mchenry